Bit error rate test

A testing method for digital communication circuits that uses predetermined stress patterns consisting of a sequence of logical ones and zeros generated by a test pattern generator.

BERT or bit error rate test is a testing method for digital communication circuits that uses predetermined stress patterns consisting of a sequence of logical ones and zeros generated by a test pattern generator.

A BERT typically consists of a test pattern generator and a receiver that can be set to the same pattern. They can be used in pairs, with one at either end of a transmission link, or singularly at one end with a loopback at the remote end. BERTs are typically stand-alone specialized instruments but can be personal computer-based. In use, the number of errors, if any, are counted and presented as a ratio such as 1 in 1,000,000, or 1 in 1e06.

Common types of BERT stress patterns

  • PRBS (pseudorandom binary sequence) – A pseudorandom binary sequencer of N Bits. These pattern sequences are used to measure jitter and eye mask of TX-Data in electrical and optical data links.
  • QRSS (quasi-random signal source) – A pseudorandom binary sequencer which generates every combination of a 20-bit word, repeats every 1,048,575 words, and suppresses consecutive zeros to no more than 14. It contains high-density sequences, low-density sequences, and sequences that change from low to high and vice versa. This pattern is also the standard pattern used to measure jitter.
  • 3 in 24 – Pattern contains the longest string of consecutive zeros (15) with the lowest one's density (12.5%). This pattern simultaneously stresses the minimum one's density and the maximum number of consecutive zeros. The D4 frame format of 3 in 24 may cause a D4 yellow alarm for frame circuits depending on the alignment of one bit to a frame.
  • 1:7 – Also referred to as 1 in 8. It has only a single one in an eight-bit repeating sequence. This pattern stresses the minimum one's density of 12.5% and should be used when testing facilities set for B8ZS coding as the 3 in 24 pattern increases to 29.5% when converted to B8ZS.
  • Min/max – Pattern rapid sequence changes from low density to high density. Most useful when stressing the repeater's ALBO feature.
  • All ones (or mark) – A pattern composed of ones only. This pattern causes the repeater to consume the maximum amount of power. If DC to the repeater is regulated properly, the repeater will have no trouble transmitting the long one's sequence. This pattern should be used when measuring span power regulation. An unframed all ones pattern is used to indicate an AIS (also known as a blue alarm).
  • All zeros – A pattern composed of zeros only. It is effective in finding equipment mis-optioned for AMI, such as fiber/radio multiplex low-speed inputs.
  • Alternating 0s and 1s - A pattern composed of alternating ones and zeroes.
  • 2 in 8 – Pattern contains a maximum of four consecutive zeros. It will not invoke a B8ZS sequence because eight consecutive zeros are required to cause a B8ZS substitution. The pattern is effective in finding equipment misoptioned for B8ZS.
  • Bridgetap - Bridge taps within a span can be detected by employing a number of test patterns with a variety of ones and zeros densities. This test generates 21 test patterns and runs for 15 minutes. If a signal error occurs, the span may have one or more bridge taps. This pattern is only effective for T1 spans that transmit the signal raw. Modulation used in HDSL spans negates the bridgetap patterns' ability to uncover bridge taps.
  • Multipat - This test generates five commonly used test patterns to allow DS1 span testing without having to select each test pattern individually. Patterns are all ones, 1:7, 2 in 8, 3 in 24, and QRSS.
  • T1-DALY and 55 OCTET - Each of these patterns contains fifty-five (55), eight-bit octets of data in a sequence that changes rapidly between low and high density. These patterns are used primarily to stress the ALBO and equalizer circuitry but they will also stress timing recovery. 55 OCTET has fifteen (15) consecutive zeroes and can only be used unframed without violating one's density requirements. For framed signals, the T1-DALY pattern should be used. Both patterns will force a B8ZS code in circuits optioned for B8ZS.

Bit error rate tester

A bit error rate tester (BERT), also known as a "bit error ratio tester"' or bit error rate test solution (BERTs) is electronic test equipment used to test the quality of the signal transmission of single components or complete systems.

The main building blocks of a BERT are:

  • Pattern generator, which transmits a defined test pattern to the DUT or test system
  • Error detector connected to the DUT or test system, to count the errors generated by the DUT or test system
  • Clock signal generator to synchronize the pattern generator and the error detector
  • Digital communication analyzer is optional to display the transmitted or received signal
  • Electrical-optical converter and optical-electrical converter for testing optical communication signals
  • BERT
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Last modified on August 4, 2020, 5:11 am is a service provided by Codecide, a company located in Chicago, IL USA.