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Clock skew

A phenomenon in synchronous digital circuit systems (such as computer systems) in which the same sourced clock signal arrives at different components at different times.

Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital circuit systems (such as computer systems) in which the same sourced clock signal arrives at different components at different times. The instantaneous difference between the readings of any two clocks is called their skew.

The operation of most digital circuits is synchronized by a periodic signal known as a "clock" that dictates the sequence and pacing of the devices on the circuit. This clock is distributed from a single source to all the memory elements of the circuit, which for example could be registers or flip-flops. In a circuit using edge-triggered registers, when the clock edge or tick arrives at a register, the register transfers the register input to the register output, and these new output values flow through combinational logic to provide the values at register inputs for the next clock tick. Ideally, the input to each memory element reaches its final value in time for the next clock tick so that the behavior of the whole circuit can be predicted exactly. The maximum speed at which a system can run must account for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.

In a synchronous circuit, two registers, or flip-flops, are said to be "sequentially adjacent" if a logic path connects them.

Confusion between clock skew and clock jitter

In addition to clock skew due to static differences in the clock latency from the clock source to each clocked register, no clock signal is perfectly periodic, so that the clock period or clock cycle time varies even at a single component, and this variation is known as clock jitter. At a particular point in a clock distribution network, jitter is the only contributor to the clock timing uncertainty.

As an approximation, it is often useful to discuss the total clock timing uncertainty between two registers as the sum of spatial clock skew (the spatial differences in clock latency from the clock source), and clock jitter (meaning the non-periodicity of the clock at a particular point in the network). Unfortunately, spatial clock skew varies in time from one cycle to the next due to local time-dependent variations in the power supply, local temperature, and noise coupling to other signals.

Thus, in the usual case of sending and receiving registers at different locations, there is no clear way to separate the total clock timing uncertainty into spatial skew and jitter. Thus some authors use the term clock skew to describe the sum of spatial clock skew and clock jitter. This, of course, means that the clock skew between two points varies from cycle to cycle, which is a complexity that is rarely mentioned. Many other authors use the term clock skew only for the spatial variation of clock times and use the term clock jitter to represent the rest of the total clock timing uncertainty. This, of course, means that the clock jitter must be different at each component, which again is rarely discussed.

Fortunately, in many cases, spatial clock skew remains fairly constant from cycle to cycle, so that the rest of the total clock timing uncertainty can be well approximated by a single common clock jitter value.

On a network

On a network such as the internet, clock skew describes the difference in frequency (first derivative of offset with time) of different clocks within the network. Network operations that require timestamps that are comparable across hosts can be affected by clock skew. A number of protocols (e.g. Network Time Protocol) have been designed to reduce clock skew, and produce more stable functions. Some applications (such as game servers) may also use their own synchronization mechanism to avoid reliability problems due to clock skew.

Interfaces

Clock skew is the reason why at fast speeds or long distances, serial interfaces (e.g. Serial Attached SCSI or USB) are preferred over parallel interfaces (e.g. parallel SCSI).

Key Terms

circuit
clock
clock jitter
clock skew
cycle
network
register
registers
skew
total clock

Additional Resources

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Acronymn

(none found)

Synonymns

Clock skew
Timing skew
Clock phase deviation

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Sources & Credits

Last modified on February 2 2020
Content adapted from Wikipedia
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